ACS11001 Digital and Embedded Systems
Assignment 2023/24
Assignment weighting
25%
Assignment released
10 November 2023
Assignment Due
4 p.m., Friday, 8 December 2023. You must submit the completed assignment to the ACS11001
Blackboard page as a single PDF document via the Assignment link in the Assessment folder. You must
include ONLY your registration number on the title page.
Feedback
Detailed mark sheets and written feedback will be provided no later than Friday 12 January 2024. The
mark sheet at the end of this document provides a guide to what areas the feedback will be provided
on. Note that marks are provisional and may be subject to change, for example as a result of unfair
means.
Unfair Means
This is an individual assignment. The use of unfair means, e.g. plagiarism and collusion, is strictly
forbidden. Students are warned that the piece of work affected may be given a grade of zero, which
in some cases will entail failure of the module. Electronic software (e.g. Turnitin) may be used to check
for unfair means.
You should thoroughly read and understand the information at
https://www.sheffield.ac.uk/ssid/unfair-means/index, including the University’s guidance to students
on unfair means. If you are at all unsure about what this means and the implications for your work,
then you should consult the module leader.
Extenuating Circumstances
Applications for extensions to the submission date must be made by submitting an extenuating
circumstances form (google form available in the student handbook).
Please note that extensions will only be granted if a student cannot reasonably submit the assignment
within the original deadline and can provide a valid reason supported by appropriate evidence.
Typically extensions will only be granted in the event of medical and/or personal circumstances
beyond the control of the student and requests for extensions should be made as early as is feasibly
possible. Failure to have backed-up your data and poor planning so that everything is being done at
the last minute are not valid reasons.
Submission Format
The assignment should be submitted as a single PDF document. There is no page limit or particular
requirements for font types, size, page margins and line spacing. However, it is suggested that you use
2
either Times New Roman or Calibri and 1**point type with at least 2cm margins at the top and bottom
of the page and 1.5 line spacing.
All diagrams (e.g. truth table, Karnaugh map, logic circuit) must be professionally produced, not hand
drawn. You may use online tools e.g. an online K-map solver, although you are encouraged to solve
for minimal expressions by drawing the map, grouping cells and finding the minimal terms yourself as
this will stand you in good stead for answering questions requiring the use of the Karnaugh map
technique in the invigilated examination. Ensure that all diagrams are neat and appropriately labelled.
Help
This document should provide all the information that is required to complete this assignment. It is
not expected that you should need to ask further questions. This is an assessment so you should not
discuss solutions with or seek help from others including the module instructors and Graduate
Teaching Assistants. However, if you feel that any part of this document is not clear, you may post
your question on the Discussion Board on Blackboard. Remember that you need to clearly present the
procedure that you followed to solve every question of the assignment. This is part of what you are
being assessed on besides your knowledge and understanding of the module and problem-solving
skills.
Marking Criteria
See attached marking criteria – this is the mark sheet that will be used to assess the assignment. The
mark sheet indicates some of the factors that will be used in assessing the assignment.
Penalties for Late Submission
Late submissions will incur the usual penalties of a 5% reduction in the mark for every working day (or
part thereof) that the assignment is late and a mark of zero for submission more than 5 working days
late.
3
Assignment Questions (total of 2 questions)
Question 1
You are working as an embedded systems engineer and have been tasked to design a burglar alarm
system for a storeroom in a house. Inside the storeroom, there is a steel safe where the house owner
keeps their money, jewellery and important documents. The logic circuit that you will design should
have between two to 5 input lines and one output line that activates the alarm when it is at logic 1.
The inputs indicate the state of the sensors which you will select and briefly describe their functions.
(i) Write the logical statements describing the conditions of the inputs that would activate
the alarm.
(ii) Assign a meaningful letter to each input variable in the statement e.g. D for storeroom
door.
(iii) Write a Boolean expression in a minimal form for the alarm activation.
(iv) Using an online tool (e.g. https://logic.ly/demo/samples) draw the logic circuit that
implements the expression found.
[10 marks]
Question 2
Figure Q2a below shows a counting process based on the binary number system. A detection system
based on an infrared transmitter-receiver (not shown) causes pulses to be sent to the system when
the receiver does not detect the transmitted pulse. Each time a pulse is received, the count increases.
The binary number produced is sent to a decoder to produce signals that will control the display of
the count as a decimal digit on the LED screen. The screen can only show a maximum of 9 balls that
have fallen into the box.
You are tasked to modify the system in two ways:
(i) The LED screen is to display the count using the hexadecimal digits (0 – F) instead of the
decimal digits (0 – 9). The hexadecimal digits should be displayed as shown in Figure 2b.
(ii) The maximum count is to be increased to 24 balls. This means you need a LED screen with
two digits. The decoder shown in Figure 2b must be modified.
Design the decoder to convert its input, the binary codes, to the outputs required to drive a two-digit
LED screen. Besides the input ABCD (A is the most significant bit and complements for all input
variables are not available), the decoder has a control signal S (not shown in the figures below) which
is normally high for the display to turn on. When it goes low, the display turns off.
Provide a brief explanation of your overall design concept. You should illustrate your design, based on
the diagrams provided, using high-level schematics, e.g. a block diagram with blocks for each
component. Label them clearly including their inputs and outputs.
State whether you are using positive or negative logic. Using appropriate methods, for example, truth
table and Karnaugh map, find the minimal logic expressions for the outputs of the decoder. You do
4
not need to show the internal structure of the decoder (i.e., you do not need to show the logic gate
implementation of the decoder).
Evaluate the designed system's current function and limitations, as well as how robust the system is
to future extensions. One possible future extension would be the increase in maximum balls to be
counted to 300, but you are encouraged to consider other possibilities.
[10 marks]
Question 2
A seven-segment display is widely used in electronic devices such as digital clocks, electronic meters
and others that display numerical information. You are asked to design a HEX-to-7-segment decoder.
Besides the input WXYZ (W is the most significant bit and complements for all input variables are not
available), the decoder has a control signal S (not shown in the schematic below) which is normally
Figure 2a. Illustration of a counting process using the binary and decimal number systems.
[Source: Digital Fundamentals by T. Floyd]
HEX-to-7-segment
decoder
led display
Figure 2b. The decoder and the 7-segment LED display, including how the hexadecimal numbers (0 –
F) will be displayed.
[15 marks]
5
ACS11001 Digital and Embedded Systems
Assignment Autumn Semester 2023/24
Marking and Feedback Sheet
Student Registration No …………………………………….............................................
Marking Criterion/Comments Marks
Question 1
Up to 3 marks for choice of sensors.
Up to 2 marks for logical statements.
Up to 2 marks for deriving the minimal logical expression.
Up to 3 marks for circuit implementation.
/10
Question 2:
Up to 8 marks for an explanation of the overall design (this can include a diagram
to illustrate the design) and an evaluation of the system’s function and possible
future extension.
Up to 7 marks for a truth table, Karnaugh map or other appropriate method(s) for
illustrating the function of the modified decoder.
請(qǐng)加QQ：99515681 或郵箱：99515681@qq.com WX：codehelp
